View Z89166_27429.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
CUSTOMER PROCUREMENT SPECIFICATION
Z89165/167/169 AND Z89166/168 (ROMLESS)
ENHANCED DUAL-PROCESSOR DTAD CONTROLLERS
FEATURES
s Part Number Z8 ROM (KBytes) Z8 RAM* (KBytes)
236 236 236 236 236
Speed (MHz)
20 20 24 24 24
s s
25 Expanded Register Files 47 Input/Output Lines (Z89165) 31 Input/Output Lines (Z89166) 43 Input/Output Lines (Core Processor) Six Vectored, Prioritized Z8 Interrupts with Programmable Polarity Three Vectored, Prioritized DSP Interrupts with Programmable Polarity Two Analog Comparators Two Programmable Z8 8-Bit Counter/Timers, Each with Two 6-Bit Programmable Prescaler Watch-Dog Timer /Power-On Reset On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive RAM and ROM Protect, Low-EMI Option
Z89165 24 Z89166 ROMless Z89167 24 Z89168 ROMless Z89169 32 *General-Purpose
s
s
Part Number
Z89165 Z89166 Z89167 Z89168 Z89169
DSP ROM (Words)
6K 6K 8K 8K 8K
DSP RAM (Words)
512 512 512 512 512
Speed (MHz)
20 20 24 24 24
s
s s
s s s s
68- and 84-Pin PLCC Packages 4.5- to 5.5-Volt Operating Range Low-Power Consumption (200 mW Typical)
s s
s 0C to +70C Temperature Range
GENERAL DESCRIPTION
Zilog's Digital Voice Processor Controller family combines a Z8(R) microcontroller and a DSP processor on-chip for a cost-effective turnkey system in digital telephone answering devices and other voice processing applications. The dual-processor architecture is loosely coupled by mailbox registers and an interrupt system, enabling DSP or Z8 programs to be directed by events in each other's domain. The Z8 microcontroller uses an expanded register file to allow access to register-mapped peripheral and I/O circuits for programming versatility. The 16-bit DSP processor features a 24-bit ALU and accumulator with single-cycle instructions, providing the algorithm processing power necessary for telephone voice quality. The Z89165/166 devices offer a half-flash 8-bit A/D converter with up to 128 kHz sample rate and a 10-bit Pulse-Width modulator (PWM) D/A converter, eliminating the need for an external CODEC. The Z89167/168/169 devices feature a hardware ARAM interface, as well as a dual-CODEC interface. A 10-bit PWM D/A converter is also on-chip.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
CP96TAD0103
1
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
GENERAL DESCRIPTION (Continued)
P00 P01 P02 P03 Port 0 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 Register Bus 24 Kbytes Program ROM (Z89165) Internal Address Bus Z8 Core Internal Data Bus Expanded Register Bus Port 4 P40 P41 P42 I/O P43 (Bit P44 Programmable) P45 P46 P47 Timer 0 Capture Reg. Timer 1 Register File 256 x 8 Bit Port 3 P31 P32 P33
Address or I/O (Nibble Programmable)
Input
P34 P35 Output P36 P37
Address/Data or I/O (Byte Programmable)
Port 1
Expanded Register File (Z8)
Peripheral Register (DSP)
Extended Bus of the DSP
mailbox
Port 2
256 Word RAM 0
256 Word RAM 1 Port 5
I/O (Bit Programmable)
Internal Address Bus 6K Words Program ROM Internal Data Bus INT 1 DSP Core
P50 P51 P52 P53 P54 P55 P56 P57
I/O (Bit Programmable)
RMLS /AS /DS R/W XTAL1 XTAL2 VDD GND /RESET
INT 2 Ext. Memory Control DSP Port Extended Bus of the DSP Timer 2 Timer 3 PWM (10-Bit) OSC
DSP0 DSP1
PWM
Power
ADC (8-Bit)
AN IN AN VDD AN GND VREF+ VREF-
Z89165/166 Functional Block Diagram
2
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
GENERAL DESCRIPTION (Continued)
P00 P01 P02 P03 Port 0 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Internal Register Bus 24 Kbytes (167) 32 Kbytes (169) Program ROM Timer0 Timer1 Register File 256 x 8-Bit Port 4 P40 P41 P42 I/O P43 (Bit P44 P45 Programmable) P46 P47 P50 I/O P51 (Bit P52 Programmable) P53
Address or I/O (Nibble Programmable)
Z8 Core
Address/Data or I/O (Byte Programmable)
Port 1
Internal Address Bus Internal Data Bus
Port 5
Address Bus P20 P21 P22 P23 P24 P25 P26 P27 8K Words Program ROM Port 2 Data Bus Peripheral Data Bus of the DSP Mailbox Peripheral Registers (DSP) Port 3 Extended Register File (Z8) ARAM Controller DSP Core Data0 Data1 Data2 Data3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ARAM_SEL0 ARAM_SEL1 /RAS /CAS ARAM_R/W ARAM_/OE /RESET VDD GND
I/O (Bit Programmable)
P31 Input P32 P33 P34 Output P35 P36 P37
DIN DENA0 DCLK DOUT DENA1
ARAM Control CODEC Interface Power
RMLS /AS /DS R/W
Z8 EXT. Memory Control Timer3 Timer2
-5V Control
Out -5V
PWM
PWM (10-Bit)
OSC
XTAL1 XTAL2
Z89167/168/169 Functional Block Diagram
CP96TAD0103
3
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
PIN DESCRIPTION
ANVDD RMLS GND VDD P00 P01 P02 P03 P57 P50 P04 P51 P52 P21 P20 P07 /DS ANVDD GND VDD VDD P00 P01 P02 P03 P57 P50 P04 P51 P52 P21 P20 P07 /DS
9 XTAL2 XTAL1 P22 P56 P23 P55 P54 GND P17 P05 P24 P16 P25 P15 P26 P27 N/C 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 VREF+ ANIN VREFANGND /AS /RESET R//W PWM P10 P47 P11 P46 P53 P45 P44 P43 N/C
9 XTAL2 XTAL1 P22 P56 P23 P55 P54 GND P17 P05 P24 P16 P25 P15 P26 P27 SCLK 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 VREF+ ANIN VREFANGND /AS /RESET R//W PWM P10 P47 P11 P46 P53 P45 P44 P43 /SYNC
Z89165
53 52 51 50 49 48 47 46 45
Z89166
53 52 51 50 49 48 47 46 45
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
P31
P32
P33
P34
P35
P14
P36
P13
P37
P40
P12
P06
P41
DSP1
DSP1
Z89165 68-Pin PLCC Pin Identification
DSP0
Z89166 68-Pin PLCC Pin Identification
Pin Identification Pin Name +5V GND AN Vref- Vref+ AN VDD AN GND P00-P07 Data P10-P17 Data P20-P27 Data Function Direction Power Power AIN AIN AIN Power Power I/O I/O I/O 5V Power Input (Digital Power) Device Ground (Digital Ground) 8-Bit A to D Converter Input Low Reference Level for A to D Converter High Reference Level for A to D Converter ADC +5V Power (Analog Power) ADC Ground (Analog Ground) General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port Pin Name Function Direction General-Purpose I/O Port General-Purpose I/O Port General-Purpose I/O Port General-Purpose 0 Port 20.48 MHz Crystal Oscillator Input 20.48 MHz Crystal Oscillator Input System RESET 10-Bit PWM, 5V TTL Output
P31-P37 Data I/O P40-P47 Data I/O P50-P57 Data I/O DSP0-DSP1 Data 0 XTAL1 OSC1 XTAL2 /RESET PWM OSC2 I/O Out
4
DSP0
P31
P32
P33
P34
P35
P14
P36
P13
P37
P40
P12
P06
P41
VDD
P42
VDD
CP96TAD0103
P42
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
PIN DESCRIPTION (Continued)
XTAL1 XTAL2 P27 P26 P25 P24 P23 P41 P40 C_DIN C_DOUT P22 P21 P20 P47 P46 P45 P44 P43 P42 /DS
VCC ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ARAM_SEL0 ARAM_SEL1 DATA0 DATA1 DATA2 DATA3 /RAS /CAS GND
11 12
1 84
75 74
VCC C_CLOCK C_EN0 C_EN1 P50 P51 P52 P53
Z89168 84-Pin PLCC
OUT_5V GND /AS P37 P36 P35 P34 P33 P32 P31 PWM P10 GND
32 33
ARAM_R/W /RESET P07 P06 P05 P04 P03 ARAM_OE
54 42 43
P02 P01 P00 P17 P16 P15 P14 VCC VCC R/W P13
53
P12 P11
Z89168 84-Pin PLCC Pin Identification
CP96TAD0103
5
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
PIN DESCRIPTION (Continued)
Z89168 84-Pin PLCC Pin Identification I/O Port Functions VSS VCC P00-P07 P10-P17 P20-P27 P31-P37 P40-P47 P50-P53 C_DIN C_DOUT C_CLOCK C_ENA0 C_ENA1 PWM DATA0 DATA1 DATA2 DATA3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 Pin Number 32, 54, 65 12, 44, 74, 45 43-36 55, 53-51, 49-46 2-9 57-63 77-84 70-67 76 75 73 72 71 56 26 27 28 29 13 14 15 16 17 18 19 20 21 22 23 Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Output Output Output Output Output Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Output Output Output I/O Function Digital Ground Digital VCC = +5 V P00-P07 (General-purpose nibble programmable I/O port.) P10-P17 (General-purpose byte programmable I/O port.) P20-P27 (General-purpose bit programmable I/O.) P31-P37 (General-purpose I/O port. Bits P31-P33 are inputs, while bits P34-P37 are outputs.) P40-P47 (General-purpose bit programmable I/O.) P50-P53 (General-purpose bit programmable I/O.) Data input from CODEC. Data output to CODEC. CODEC clock (2.048 MHz) CODEC 0 enable (8 kHz) CODEC 1 enable (8 kHz) Pulse Width Modulator output Data 0 I/O of the ARAM Interface Data 1 I/O of the ARAM Interface Data 2 I/O of the ARAM Interface Data 3 I/O of the ARAM Interface Address 0 line of the ARAM Interface Address 1 line of the ARAM Interface Address 2 line of the ARAM Interface Address 3 line of the ARAM Interface Address 4 line of the ARAM Interface Address 5 line of the ARAM Interface Address 6 line of the ARAM Interface Address 7 line of the ARAM Interface Address 8 line of the ARAM Interface Address 9 line of the ARAM Interface Address 10 line of the ARAM Interface for 4 Meg ARAMs. Select 2 output of ARAM Interface for 1 Meg ARAMs support. The latter mode is used to switch between different pages of ARAM. Select 0 output of ARAM Interface. Used to switch between different pages of ARAM. Select 1 output of ARAM Interface. Used to switch between different pages of ARAM. Row Address Strobe of ARAM Interface. Column Address Strobe of ARAM Interface. Read/Write Strobe of ARAM Interface. Output Enable Strobe of ARAM Interface. 24.57 MHz crystal input 24.57 MHz crystal output /RESET input Z8 (R) external memory interface R/W output Z8 external memory interface /AS output Z8 external memory interface /DS output
ARAM_SEL0 ARAM_SEL1 /RAS /CAS ARAM_R/W ARAM_/OE XTAL1 XTAL2 /Reset R/W /AS /DS
24 25 30 31 34 33 11 10 35 50 64 1
Output Output Output Output Output Output Input Output Input Output Output Output
6
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
PIN DESCRIPTION (Continued)
XTAL1 XTAL2 P27 P26 P25 P24 P23 P41 P40 C_DIN C_DOUT
P22 P21 P20
P47 P46 P45 P44
VCC ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ARAM_SEL0 ARAM_SEL1 DATA0 DATA1 DATA2 DATA3 /RAS /CAS GND
11 12
1 84
P43 P42
/DS
75 74
VCC C_CLOCK C_EN0 C_EN1 P50 P51 P52 P53
Z89C169/Z89C167 84-Pin PLCC
OUT_5V GND /AS P37 P36 P35 P34 P33 P32 P31 PWM P10 GND
32 33
ARAM_R/W /RESET P07 P06 P05 P04 P03 ARAM_OE
54 42 43
P02 P01 P00 P17 P16 P15 P14 VCC RMLS R/W P13
53
P12 P11
Z89167/169 84-Pin PLCC Pin Identification
CP96TAD0103
7
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
PIN DESCRIPTION (Continued)
Z89169/Z89167 84-Pin PLCC, Pin Identification I/O Port Functions VSS VCC P00-P07 P10-P17 P20-P27 P31-P37 P40-P47 P50-P53 C_DIN C_DOUT C_CLOCK C_ENA0 C_ENA1 PWM DATA0 DATA1 DATA2 DATA3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 Pin Number 32, 54, 65 12, 44, 74 43-36 55, 53-51, 49-46 2-9 57-63 77-84 70-67 76 75 73 72 71 56 26 27 28 29 13 14 15 16 17 18 19 20 21 22 23 Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Output Output Output Output Output Input/Output Input/Output Input/Output Input/Output Output Output Output Output Output Output Output Output Output Output Output I/O Function Digital Ground Digital VCC = +5 V P00-P07 (General-purpose nibble programmable I/O port.) P10-P17 (General-purpose byte programmable I/O port.) P20-P27 (General-purpose bit programmable I/O.) P31-P37 (General-purpose I/O port. Bits P31-P33 are inputs, while bits P34-P37 are outputs.) P40-P47 (General-purpose bit programmable I/O.) P50-P53 (General-purpose bit programmable I/O.) Data input from CODEC. Data output to CODEC. CODEC clock (2.048 MHz) CODEC 0 enable (8 kHz) CODEC 1 enable (8 kHz) Pulse Width Modulator output Data 0 I/O of the ARAM Interface Data 1 I/O of the ARAM Interface Data 2 I/O of the ARAM Interface Data 3 I/O of the ARAM Interface Address 0 line of the ARAM Interface Address 1 line of the ARAM Interface Address 2 line of the ARAM Interface Address 3 line of the ARAM Interface Address 4 line of the ARAM Interface Address 5 line of the ARAM Interface Address 6 line of the ARAM Interface Address 7 line of the ARAM Interface Address 8 line of the ARAM Interface Address 9 line of the ARAM Interface Address 10 line of the ARAM Interface for 4 Meg ARAMs. Select 2 output of ARAM Interface for 1 Meg ARAMs support. The latter mode is used to switch between different pages of ARAM. Select 0 output of ARAM Interface. Used to switch between different pages of ARAM. Select 1 output of ARAM Interface. Used to switch between different pages of ARAM. Row Address Strobe of ARAM Interface. Column Address Strobe of ARAM Interface. Read/Write Strobe of ARAM Interface. Output Enable Strobe of ARAM Interface. 24.57 MHz crystal input 24.57 MHz crystal output Z8 (R) Romless mode input (P0 and P1 are switched to D/A mode if this pin is connected to VCC). Internally this pin is tight to GND. /RESET input/output Z8 external memory interface R/W output Z8 external memory interface /AS output Z8 external memory interface /DS output CP96TAD0103
ARAM_SEL0 ARAM_SEL1 /RAS /CAS ARAM_R/W ARAM_/OE XTAL1 XTAL2 ROMLESS /Reset R/W /AS /DS 8
24 25 30 31 34 33 11 10 45 35 50 64 1
Output Output Output Output Output Output Input Output Input InputOutput Output Output Output
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
ABSOLUTE MAXIMUM RATINGS
Symbol V CC TSTG TA Description Min Max +7.0 +150 2.2 Units V C C W Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Supply Voltage (*) -0.3 Storage Temp -65 Oper Ambient Temp Power Dissipation
Notes: * Voltage on all pins with respect to GND. See Ordering Information.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram).
From Output Under Test
+5V
2.1 k
150 pF 9.1 k
Test Load Diagram
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins to GND. Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF
DC ELECTRICAL CHARACTERISTICS
VCC Note [1] 5.0 V 5.0 V TA = 0C to +70C Min Max 65 20 Typical @ 25C 40 6
Sym ICC ICC1 ICC2
Parameter Supply Current Halt Mode Current Stop Mode Current
Units mA mA
Notes
[2]
Notes: [1] 5.0V 0.5V. [2] The typical Stop Mode Current value is 500 A. The transient characteristics of the Stop Mode Current will vary according to the application and should be validated in the specific application by the customer.
CP96TAD0103
9
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
DC ELECTRICAL CHARACTERISTICS Z89165/Z89166
TA = 0 C to +70 Min Max 0.9 VCC GND-0.3 0.7 VCC GND-0.3 VCC-0.4 7 VCC+0.3 0.1 VCC VCC+0.3 0.2 VCC 0.4 1.2 Typical @ 25C 2.5 1.5 2.5 1.5 4.8 0.1 0.3
Sym Parameter VMAX VCH VCL VIH VIL VOH VOL1 VOL2 Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage
VCC Note [1] 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V
Units V V V V V V V V
Conditions IIN = 250 A Driven by External Clock Generator Driven by External Clock Generator
IOH = -2.0 mA (Does not include XTAL2) IOH = +4.0 mA IOL = +12 mA, 3 Pin Max
(Does not include XTAL2) VRH VRl Reset Input High Voltage Reset Input Low Voltage 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V -5 -5 0.8 VCC GND-0.3 VCC 0.2 VCC 25 5 5 -55 2.1 1.7 10 <5 <5 -30 V V mV A A A VIN = OV, VCC VIN = OV, VCC
VOFFSET Comparator Input Offset Voltage IIL Input Leakage IOL IIR Output Leakage Reset Input Current
Notes: [1] 5.0 10% (V).
10
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
Z891650A ADDITIONAL DC ELECTRICAL CHARACTERISTICS
1. A/D CONVERTER: ABSOLUTE INPUT CURRENT VALUES Symbol Iil Iih Iinput Iinput Parameter Anin Anin Vref+ Vref- Maximum 40 A 2 A 1.1 mA 80 A 1.1 mA 80 A Notes
With Vref- = 0V With Vref- = Vref+ With Vref+ = 5.5V With Vref+ = Vref+
Vref+ = 5.5V Vref+ = 5.5V Vref- = 0V Vref- = 0V
The following parameters should be verified on the ATE under these conditions: 5.5V @ 25C.
2. OTHER PINS Pin Under Test V a l u e 6 A 6 A 1mA 30 A 30 A 10 A 10 A 1 mA 1 mA 4 mA 4 mA 2 mA -1mA 7 mA 6mA 1 A 1 A Additional No Reset No Reset During Reset While XTAL2 = 0V While XTAL2 = 5.5V While XTAL1 = 0V While XTAL2 = 5V While XTAL1 = 0V While XTAL2 = 5V While XTAL1 = 0V While XTAL2 = 5V VOL = 1V VOH = VDD -1V VOL = 1V VOH = VDD -1V No Reset No Reset Stop Mode Invoked Stop Mode Invoked No Reset No Reset During Reset During Reset VDD = 4.5V Temp = 70C VDD = 4.5V Temp = 70C VDD = 5.5V Temp = 0C VDD = 5.5V Temp = 0C Condition
Romless Pin Iih(max) = Iil (max) = Iih(max) = XTAL1 Iih(max) = Iil (max) = XTAL2 Iih(max) = Iil (max) = Iih (max) = Iil (max) = Iih(max) = Iil (max) = IOL(min) = IOH(min) = IOL(max) = IOH(max) = P31, P32, P33 Iih(max) = (max) =
CP96TAD0103
11
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
DC ELECTRICAL CHARACTERISTICS Z89167/168/169
TA = 0 C to +70C Sym Parameter Max Input Voltage VCH VCL VIH VIL VOH VOL1 VOL2 VRH VRl VOFFSET IIL IOL IIR Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltge Output Low Voltage Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Comparator Input Offset Voltage Input Leakage Output Leakage Reset Input Current VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Min Max 7 7 VCC+0.3 VCC+0.3 0.1 VCC 0.1 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
Typical Units 25C at V V V V V V V V V V V V V V V V V V
Conditions IIN 250 uA IIN 250 uA Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
0.9 VCC 0.9 VCC GND-0.3 GND-0.3 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC-0.4 0.6 0.4 1.2 1.2 .8 VCC .8 VCC GND-0.3 GND-0.3
1.3 2.5 0.7 1.5 1.3 2.5 0.7 1.5 3.1 4.8 0.2 0.1 0.3 0.3
IOH = -2.0 mA IOH = -2.0 mA IOH = +4.0 mA IOL = +4.0 mA IOL = +6 mA, 3 Pin Max IOL = +12 mA, 3 Pin Max
[1]
VCC VCC 0.2 VCC 0.2 VCC 25 25 5 5 5 5 -45 -55
1.5 2.1 1.1 1.7 10 10 <5 <5 <5 <5 -20 -30
-5 -5 -5 -5
mV mV A A A A A A
VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
Note: [1] P10, P11 are measured at 4.5V only.
12
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram
R//W
13 12
Port 0, /DM
16 19 3
Port 1
A7 - A0
1 2
D7 - D0 IN
9
/AS
8 4 5 6 18 11
/DS (Read)
17
10
Port1
A7 - A0
14
D7 - D0 OUT
15 7
/DS (Write)
External I/O or Memory Read/Write Timing
CP96TAD0103
13
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC CHARACTERISTICS Z89165/166 External I/O or Memory Read and Write Timing Table
VCC Note [4] 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V TA=0C to +70C Min Max 25 35 150 35 -3 125 75 90 0 40 35 25 35 40 25 180 48 50 20
No Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS)
Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [2,3]
TdDS(R/W) /DS Rise to R//W Not Valid TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay TdDS(DW) TdA(DR) TdAS(DS) TdDI(DS) TdDM(AS) /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Fall Delay
Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. [4] 5.0 V 0.5 V. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
14
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC CHARACTERISTICS Z89167/168/169 External I/O or Memory Read and Write Timing Table
VCC Note [4] 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V TA=0C to +70C Min Max 18 22 130 28 0 90 62 55 0 36 25 18 22 18 23 160 32 28 18
No Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS)
Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [2,3]
TdDS(R/W) /DS Rise to R//W Not Valid TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay TdDS(DW) TdA(DR) TdAS(DS) TdDI(DS) TdDM(AS) /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Fall Delay
Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. [4] 5.0 V 0.5 V. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
CP96TAD0103
15
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram
1 3
Clock
2 7 7 2 3
TIN
4 6 5
IRQN
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Additional Timing
16
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC ELECTRICAL CHARACTERISTICS Z89165/166 Additional Timing Table
No Symbol 1 2 3 4 5 6 7 TpC TrC,TfC TwC TwTinL TwTinH TpTin Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time Stop-Mode Recovery Width Spec Oscillator Startup Time Watch-Dog Timer VCC Note [6] 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 70 3TpC 3TpC 12 5TpC 5TpC 3 6 12 50 ns TA=0C to +70C Min Max 48.83 6 17 70 3TpC 8TpC 100 ns ns Units ns ns ns ns Notes [1] [1] [1] [1] [1] [1] [1,2] [1] [1] [1] [3] ms ms ms ms D1=0, D0 = 0 [4] D1=0, D0 = 1 [4] D1=1, D0 = 0 [4] D1=1, D0 = 1 [4]
TrTin, TfTin 8A TwIL 8B TwIL 9 TwIH 10 Twsm 11 Tost 12 Twdt
Notes: [1] Timing Reference uses 0.9 V CC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] SMR-D5 = 0. [4] Reg. WDT. [5] 5.0V 0.5V.
CP96TAD0103
17
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC ELECTRICAL CHARACTERISTICS Z89167/168/169 Additional Timing Table
VCC Note [5] 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 70 3TpC 3TpC 12 5TpC 5TpC 5 15 25 100 ns TA=0C to +70C Min Max 41.67 6 16 70 3TpC 8TpC 100 ns ns
No Symbol 1 2 3 4 5 6 7 8A 8B 9 10 11 12 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TfTin TwIL TwIL TwIH Twsm Tost Twdt
Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time Stop-Mode Recovery Width Spec Oscillator Startup Time Watch-Dog Timer
Units ns ns ns ns
Notes [1] [1] [1] [1] [1] [1] [1,2] [1] [1] [1] [3]
ms ms ms ms
D1=0, D0 = 0 [4] D1=0, D0 = 1 [4] D1=1, D0 = 0 [4] D1=1, D0 = 1 [4]
Notes: [1] Timing Reference uses 0.9 V CC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] SMR-D5 = 0. [4] Reg. WDT. [5] 5.0V 0.5V.
18
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams
Data In
Data In Valid
2 1 3
Next Data In Valid
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
CP96TAD0103
19
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
AC ELECTRICAL CHARACTERISTICS Z89165/166 Handshake Timing Table
VCC Note [1] 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V TA=0C to +70C Min Max 0 0 40 70 40 0 TpC 0 70 40 40 Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT
No Symbol 1 2 3 4 5 6 7 8 TsDI(DAV) ThDI(RDY) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdDO(DAV) TcLDAV0(RDY) TcLDAV0(RDY)
Parameter Data In Setup Time RDY to Data Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay
Units ns ns ns ns ns ns ns ns ns ns ns
9 TdRDY0(DAV) 10 TwRDY 11 TdRDY0d(DAV)
Notes: [1] 5.0 V 0.5 V
AC ELECTRICAL CHARACTERISTICS Z89167/168/169 Handshake Timing Table
VCC Note [1] 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V TA=0C to +70C Min Max 0 0 110 115 80 0 25 0 115 80 80 Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT
No Symbol 1 2 3 4 5 6 7 8 TsDI(DAV) ThDI(RDY) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdDO(DAV) TcLDAV0(RDY) TcLDAV0(RDY)
Parameter Data In Setup Time Ready to Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay
Units ns ns ns ns ns ns ns ns ns ns ns
9 TdRDY0(DAV) 10 TwRDY 11 TdRDY0d(DAV)
Notes: [1] 5.0 V 0.5 V
20
CP96TAD0103
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
ELECTRICAL CHARACTERISTICS Z89165/166 A/D CONVERTER
A/D Converter Electrical Characteristics V CC = 5.0V 10% Parameter Resolution Integral non-linearity Differential non-linearity Zero Error at 25C Supply Range Input voltage range Conversion time Input capacitance on ANA VAHI range VALO range VAHI --VALO
Notes: Voltage 4.5V -5.5V Temp 0-70C
Minimum
Typical 8 0.5 0.5 5.0
Maximum 1 1 250 5.5 VAHI 2 60 AVCC AVCC-2.5 AVCC
Units Bits LSB LSB mV Volts Volts sec pF Volts Volts Volts
4.5 VALO 25 VALO +2.5 ANGND 2.5
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com
CP96TAD0103
21
ZILOG
Z89165/166/167/168/169 DTAD CONTROLLERS
22
CP96TAD0103

▲Up To Search▲

Price & Availability of Z89166

	To Download Z89166 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .